Cagla SarvanMustafa GunduzalpGunduzalp, MustafaSarvan, Cagla2025-10-062019978-1-7281-2868-9978172812868910.1109/asyu48272.2019.89463502-s2.0-85078336446http://dx.doi.org/10.1109/asyu48272.2019.8946350https://gcris.yasar.edu.tr/handle/123456789/5839https://doi.org/10.1109/asyu48272.2019.8946350https://doi.org/10.1109/ASYU48272.2019.8946350This study provides an application-specific integrated circuit (ASIC) diagram of Artificial Neural Networks (ANN) with module design for 32-bit floating point operations on Field Programmable Gate Array (FPGA). It is aimed that ANNs train operations are moved from software to hardware and calculations are made by using IEEE 754 single precision floating point number format. The proposed architecture is designed with combination of Verilog and Very High Speed Integrated Circuits Hardware Description Language (VHDL). Sigmoidal non-linear function was used as the activation function of the train and look-up table (LUT) was created for process efficiency of the designed circuit. Natural parallelisms were used in the calculation of the operations which are implemented on FPGA thus the system operations was accelerated by performing independent operations during the same clock cycle. The results obtained from FPGA were compared with the results obtained from MATLAB R2016b.Englishinfo:eu-repo/semantics/closedAccessField Programmable Gate Array, ANN, VHDL, Verilog, single precision floating pointANNField Programmable Gate ArrayVHDLVerilogSingle Precision Floating PointConference Object